In these years, extensive studies are being made on organic thin film transistors using organic semiconductor materials. Advantages of using organic semiconductor materials in transistors include flexibility and increased areas of the transistors, a simplified fabrication process due to a simple layer structure of the transistors, and possible usage of inexpensive fabrication equipment.
In addition, by utilizing a printing method, the organic thin film transistors can be fabricated at much lower cost compared to a photolithographic technique used on silicon-based semiconductors of the related art. In addition, by using the printing method, spin-coating, or immersing, it is possible to form a thin film or circuits easily.
One of parameters indicating performance of the thin film transistor is the ratio of the current in an ON state to the current in an OFF state, usually expressed as Ion/Ioff. In the thin film transistor, a saturation current Ids flowing through a source electrode and a drain electrode is expressed by formula (1) below.Ids=μCinW(VG−Vth)2/2L  (1)
In formula (1), μ represents field effect mobility, Cin represents capacitance per unit area of a gate insulating film, W represents a channel width, L represents a channel length, VG represents a gate voltage, and Vth represents a threshold voltage.
In addition, Cin is expressed by formula (2) below.Cin=ε·ε0/d  (2)
In formula (2), ε represents specific permittivity of the gate insulating film, ε0 represents specific permittivity in a vacuum, and d represents thickness of the gate insulating film.
From the formula (1), it is clear that in order to increase the ON state current Ion, it is effective to
1. increase the field effect mobility μ,
2. shorten the channel length L,
3. increase the channel width W.
The field effect mobility μ strongly depends on material properties, and material development is being extensively made to increase the field effect mobility μ.
The channel length L is determined by the device structure, thus it is attempted to increase the ON current Ion by appropriately modifying the device structure. In the related art, it is well known that the channel length L can be shortened by shortening the distance between the source electrode and the drain electrode.
For the organic semiconductor materials, in order to increase the field effect mobility μ compared to inorganic semiconductor materials, such as silicon semiconductor, it is usually required for the channel length L be less than 10 μm, and preferably, less than 5 μm. It is known that the photolithographic technique, which is frequently used in silicon processes, is one of the methods able to precisely shorten the distance between the source electrode and the drain electrode.
Usually, a photolithographic process includes the following steps:
1. applying a photo-resist layer on a substrate having a thin-film layer (a photo-resist application step),
2. removing a solvent by heating (a pre-baking step),
3. irradiating ultraviolet rays through a hard mask, which is obtained by writing with a laser beam or an electron beam in accordance with pattern data (an exposing step),
4. removing the resist in an exposed region with an alkali solution (a developing step),
5. hardening (setting) the resist in a non-exposed region (pattern portion) by heating (a post-baking step),
6. dipping the structure fabricated so far in an etching solution or exposing the structure fabricated so far in etching gas to remove the thin-film layer in the region without the resist (an etching step), and
7. removing the resist with an alkali solution or oxygen group (a resist removing step).
After the desired thin films are formed, the above steps are repeated to complete fabrication of an electric device.
However, the photolithographic process requires expensive equipment and involves complicated fabricating steps, and thus has a long fabrication time period. These result in high fabrication cost.
In order to reduce the fabrication cost, recently, it has been attempted to form an electrode pattern by printing, such as inkjet printing. Since the electrode pattern can be directly written when using the inkjet printing, material utilization is high, and it is possible to simplify the fabrication process and reduce the cost. However, it is difficult to reduce the amount of ejected ink in the inkjet printing, and if further considering ink positioning precision, which is associated with mechanical tolerance, it is difficult to form a pattern having a dimension less than 30 μm. As a result, it is difficult to fabricate a highly precise device, like a transistor having a short channel length, with only the inkjet printing. Therefore, in order to fabricate a highly precise device, it is necessary to develop new methods, for example, it may be tried to process the surface of the substrate on which ink droplets are ejected.
For example, Japanese Laid Open Patent Application No. 2006-278534 (referred to as reference 1 below) discloses a technique of laminating films on a gate insulating film with the films formed from materials having different surface free energy levels adjusted by ultraviolet rays. According to this technique, the electrode pattern is formed on the laminated films by inkjet printing after regions having different surface free energy levels are formed by ultraviolet rays.
However, since a region having high surface free energy and a region having low surface free energy are on the same plane and separated by a boundary on the same plane, for example, when the inkjet ejection speed is high, the ink may spread over the boundary; this causes undulation of the boundary between the region having high surface free energy and the region having low surface free energy, and causes the channel length not to be clearly defined. As a result, properties of the electronic device may fluctuate.
That is, in the technique disclosed in reference 1, since the boundary between the region having high surface free energy and the region having low surface free energy is a one-dimensional line on the same plane, for example, when the inkjet ejection speed is high, the ink may spread over the boundary; this causes the channel length not to be clearly defined, and causes fluctuations of the properties of the electronic device.
For example, Japanese Laid Open Patent Application No. 2003-518332 (referred to as reference 2 below) discloses a technique of forming a three-dimensional boundary, which can be used to solve this problem. According to this technique, a polyimide bank is formed that has low surface free energy; hence the region having high surface free energy and the region having low surface free energy are not on the same plane. As a result, hydrophilic ink ejected in the region having high surface free energy is stopped by the bank, and thus the channel length is well defined.
The technique disclosed in reference 2 is superior in that the boundary between the region having high surface free energy and the region having low surface free energy is well defined by a height difference and the region having high surface free energy and the region having low surface free energy are clearly separated. However, this technique involves formation of the bank, and in order to form the bank, it is required to use the photolithographic technique which includes complicated fabricating steps, and results in high fabrication cost; consequently, advantages of fabrication of electronic devices with printing process (for example, inkjet process) are reduced.
For example, Japanese Laid Open Patent Application No. 2004-141856 (referred to as reference 3 below) discloses a technique of forming an indent instead of a bank. According to this technique, it is not required that ink droplets ejected by inkjet perfectly stop on a surface; excessive ink may spread to an indent portion, and still a well defined boundary can be formed.
The technique disclosed in reference 3 is superior in that the line able to satisfactorily stop ink is defined by an indent. However, this technique involves formation of the indent, and in order to form the indent, it is required to use the photolithographic technique which includes complicated fabricating steps and results in high fabrication cost. Consequently, advantages of fabrication of electronic devices with printing processes (for example, inkjet process) are reduced.
As described above, in the related art, a region having high surface free energy and a region having low surface free energy are formed to shorten the channel length of a thin film transistor. However, a boundary able to well separate the region having high surface free energy and the region having low surface free energy cannot be obtained, and this causes fluctuations of the properties of the electronic device. Although some methods are proposed to solve this problem, these methods require the photolithographic technique, and thus result in a complicated fabricating process and high fabrication cost, which is contrary to advantages of technique of fabricating electronic devices with printing process.
As described above, in the related art, the photolithographic technique is frequently used to form interconnection patterns in semiconductor devices and electronic circuits. Since photolithography requires expensive equipment and involves complicated fabricating processes, and thus needs a long fabrication time period, the fabrication cost increases.
In order to reduce the fabrication cost, recently, another technique of forming interconnection patterns has been attracting attention in which disperse liquid including metal particles (this liquid is referred to as “metal particle disperse liquid” below) is directly applied to a substrate.
For example, Japanese Laid Open Patent Application No. H03-281783 (referred to as reference 4 below) discloses a technique in which metal ultrafine particles of a diameter from 0.001 μm to 0.1 μm are uniformly and highly dispersed in an organic solvent to form a metal paste, the metal paste is applied on a surface of a substrate, and is dried and baked, thus forming a metal film having a thickness of 0.01 to 1 μm. Such kind of metal ultrafine particles is also called “nano-metal ink”.
However, an interconnection pattern formed from a metal particle disperse liquid, which is obtained by dispersing the nano-metal ink, namely, the metal ultrafine particles, in water or an organic solvent, has low adhesiveness to an underlying substrate compared to interconnection patterns formed by evaporation or sputtering of the related art. In addition, an electrode formed from the metal particle disperse liquid, which can be used for coating or liquid droplet ejection, is also required to have high patterning accuracy along with more and more reduced size of thin film transistors, and the adhesiveness also becomes an important issue.
Japanese Laid Open Patent Application No. 2005-159143 (referred to as reference 5 below) discloses a technique of forming an interconnection pattern by the liquid droplet ejection, which interconnection pattern is miniaturized and has good adhesiveness to a surface of a substrate. According to this technique, the interconnection pattern is formed in a region having projection and depression obtained by roughening a surface of a substrate through dry etching, frost treatment, or sandblasting which are well known in the semiconductor field related art.
However, in this technique, the projections and depressions are formed not only on the region where the interconnection pattern is formed, but also on a functional thin film which assumes the projection and depression shape of the surface of the region of the interconnection pattern; due to this, when a thin film transistor has a bottom-gate structure, the projections and depressions remain on the surface of the gate electrode, and this reduces the dielectric strength voltage and degrades the surface property of the gate insulating film formed on the gate electrode. As a result, when forming pentacene or other organic crystalline semiconductor material structures, mobility may decrease.
Japanese Laid-Open Patent Application No. 2006-114579 (referred to as reference 6 below) and Japanese Laid-Open Patent Application No. 2007-043131 (referred to as reference 7 below) disclose a technique of forming an intermediate layer between a conductive layer and an underlying layer for improving adhesiveness, which conductive layer is formed from metal particle disperse liquid including metal particles.
However, this technique involves an additional step of forming the intermediate layer, and this is contrary to the advantages of the technique of applying the metal particle disperse liquid including metal particles to a substrate directly, such as low cost and a fewer fabricating steps.
Japanese Laid-Open Patent Application No. 2003-315813 (referred to as reference 8 below) discloses a technique in which, before disposing a first liquid material including metal particles on a substrate by liquid droplet ejection means to form a conductive film interconnection having a predetermined pattern on the substrate, the surface of the substrate is controlled to be repellent to the liquid material, and a second liquid material different from the first liquid material is disposed on the substrate by the liquid droplet ejection means to form an intermediate layer for improving adhesiveness of the conductive film interconnection to the substrate.
However, by patterning utilizing liquid repellency of the substrate, it is difficult to attain sufficient adhesiveness. In addition, this technique involves an additional step of forming the intermediate layer, and this is contrary to the advantages of the technique of applying the metal particle disperse liquid including metal particles to a substrate directly, such as low cost, and fewer fabricating steps.
Japanese Laid-Open Patent Application No. 2007-012590 (referred to as reference 9 below) discloses a technique of improving adhesiveness. In this technique, after metal particle disperse liquid, which includes metal particles, water, and a solid dispersant (or dispersing agent) having a molecular weight of 2000 to 30000 and in a solid state at a room temperature, is applied on a surface of a substrate; a metal film is formed by using metal particles formed from an alloy including one or more of Ag, Au, Pt, Pd, Ru, Ir, Sn, Cu, Ni, Fe, Co, Ti, and In, in which alloy the atomic concentration of Ag is 80 to 99.9%, and an average crystal particle diameter is 0.25 μm. In this way, adhesiveness of the substrate on the coating material side is improved.
However, when forming a miniaturized interconnection, it is desirable that both the adhesiveness of the substrate on the coating material and the adhesiveness of the substrate on the side having a structure be secured, and thereby higher adhesiveness be obtained.
As described above, in the related art, although the technique of forming an interconnection pattern (conductive layer) by using the metal particle disperse liquid is proposed, there are problems in that the adhesiveness of the interconnection pattern to a substrate is not sufficient and semiconductor properties are degraded. In addition, although additional techniques are proposed to solve these problems, these techniques increase the number of fabricating steps and result in high fabrication cost.